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Instruction set architectures
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71	Advanced and parallel architectures Cognome Nome Prof. A. Massini Add to Reading List Source URL: twiki.di.uniroma1.it Language: English - Date: 2015-07-14 14:33:32 Parallel computing Advanced RISC Computing MIPS instruction set Instruction pipelining Hazard
72	Stratified Synthesis: Automatically Learning the x86-64 Instruction Set Stefan Heule Eric Schkufza Add to Reading List Source URL: raw.githubusercontent.com Language: English Instruction set architectures Central processing unit X86 instructions X86 architecture Computer architecture X86 Instruction set Processor register ARM architecture Low-level programming language NOP Intel
73	Data Sheet PRELIMINARY December 2010 AR9331 Highly-Integrated and Cost Effective IEEE 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms Add to Reading List Source URL: www.openhacks.com Language: English - Date: 2013-10-03 09:25:08 Interrupts Instruction set architectures Management Data Input/Output Central processing unit Universal asynchronous receiver/transmitter IEEE 802.11n-2009 IEEE 802.11 Control register MIPS instruction set
74	! ! ! ! CHARON-AXP/4100 for Windows Add to Reading List Source URL: www.stanq.com Language: English - Date: 2015-08-26 16:18:16 Advanced RISC Computing Instruction set architectures Charon Information technology AlphaServer Hewlett-Packard Tru64 UNIX DEC Alpha OpenVMS VAX 64-bit computing DECpc AXP 150
75	µ MOTOROLA M68000Bit Microprocessors User’s Manual Ninth Edition Add to Reading List Source URL: tict.ticalc.org Language: English - Date: 2002-08-23 04:17:08 Instruction set architectures Central processing unit Computer architecture Motorola Instruction set Addressing mode Microprocessor ARM architecture
76	yescrypt - a Password Hashing Competition submission Name of the submitted scheme: Name and email address of the submitter(s): Originally submitted on: This revision: Add to Reading List Source URL: password-hashing.net Language: English - Date: 2015-10-25 04:56:20 Computing Computer architecture Cryptography Central processing unit Parallel computing Instruction set architectures Scrypt Salsa20 SIMD ARM architecture X86 SHA-2
77	CFIMon: Detecting Violation of Control Flow Integrity using Performance Counters Yubin Xia† ‡, Yutao Liu† ‡, Haibo Chen†, Binyu Zang‡ †Institute of Parallel and Distributed Systems, Shanghai Jiao Tong Unive Add to Reading List Source URL: ipads.se.sjtu.edu.cn Language: English - Date: 2012-08-23 22:16:01 Central processing unit Machine code Software bugs Return-oriented programming Computer memory Instruction set architectures Buffer overflow protection Self-modifying code Subroutine Stack Return-to-libc attack Instruction set
78	From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware Haibo Chen† , Xi Wu† , Liwei Yuan† , Binyu Zang† , Pen-chung Yew‡ , and Frederic T. Chong§ † ‡ Add to Reading List Source URL: ipads.se.sjtu.edu.cn Language: English - Date: 2012-01-05 23:25:08 Computer architecture Computing Computer engineering Central processing unit Instruction set architectures Processor register Itanium X86 CPU cache Optimizing compiler 64-bit computing Pointer
79	Summit Press During the second annual OpenPOWER Summit, held April 5-8 in San Jose, the OpenPOWER Foundation made a set of announcements and showcased more than 50 new member innovations that advance its commitment to o Add to Reading List Source URL: openpowerfoundation.org Language: English - Date: 2016-04-25 15:50:27 Power Architecture Google IBM Nvidia OpenPOWER Foundation POWER8 Instruction set architectures IBM OpenPower Tyan Rackspace Open Compute Project Cloud computing
80	United States Market Trends as Revealed by the Top 500 Add to Reading List Source URL: lsmarr.calit2.net Language: English - Date: 2010-01-24 19:41:29 Computing Computer architecture Supercomputers Concurrent computing Distributed computing architecture Parallel computing Instruction set architectures TOP500 Silicon Graphics ASCI Red Cray 64-bit computing

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